DFT&PostSiliconValidation

ID: DFT-3

Description

As a DFT Engineer, you will collaborate in the DFT implementation process, ensuring seamless integration with test validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.

Key Responsibilities* Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.

• Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.
• Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
• Test Development & Implementation
• Develop and implement test plans and test strategies at silicon, package, and system levels.
• Define and develop automated test solutions for production and characterization.
• Ensure test coverage for all product development stages, from pre-silicon to mass production.
• Guarantee high yield on the final solution while considering chiplet complexities.
• Cross-Functional Collaboration
• Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
• Collaborate with product management to ensure alignment with customer requirements and timelines.
• Process Improvement & Innovation
• Continuously explore and implement new DFT methodologies and manufacturing processes.
• Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.

Why Seynamics? Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Se* ynamics.

• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.

Requirements

• Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.
• 4+ years of related experience

Must have - experience with Tessent and SSN methods integrated with * ing EDA design flows for advanced technology nodes is a plus.

• Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.
• Strong background in post-silicon test optimization and yield analysis.
• Experience in defining and implementing test strategies for high-volume production.
• Proficiency in RTL and testbench development using SystemVerilog and Verilog.
• Strong scripting skills (Shell, Tcl, Python3).

MID