Formal Verification Engineer
Cubane Solutions AB · Stockholm, Sweden
No Swedish requiredPosted yesterday
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Required Skills
- Formal verification of ASIC / RTL designs.
- Property checking and assertion-based verification.
- SystemVerilog / SystemVerilog Assertions.
- Debugging complex RTL and verification results.
- ASIC or SoC development environments.
Desired Skills
- UVM-based verification.
- C/C++ reference modelling.
- MATLAB.
- SystemC.